1. Field of the Invention
The present invention relates generally to processor systems, and more particularly to programmable logic technology mapping and placement.
2. Background of the Invention
Digital signal processing (DSP), encryption and other complex functions require high levels of computational power to perform the underlying intricate arithmetic operations. To improve the functionality and performance of processing such complex functions, programmable embedded systems have been implemented in electronic devices designed for specific applications. Some of these programmable embedded systems include Field Programmable Gate Array (FPGA) technology to provide programmable functions. FGPAs generally include a basic standard-cell logic disposed in a programmable array structure. FPGAs, however, are designed to be universally used in a multitude of applications and thus comprise many logic gates, such as from 400,000 to 1.5 million (or more) gates, for adaptation to a specific application. But in most applications, the large amounts of programmable logic of the FPGAs go unused and effectively become wasted.
A unique approach to providing for programmable embedded systems that minimizes unused programmable functionalities, among other things, uses one or more configurable arithmetic logic units (CALUs) disposed in rows and columns of a programmable logic array. Because CALUs provide scalable (i.e., configurable) functionality in terms of circuitry and routing resources, the programmable logic arrays having CALUs are referred to as a multi-scale programmable logic arrays (MSAs). The programmable logic core of an MSA is a programmable logic fabric that can be customized to implement any digital circuit after fabrication of, for example, a System on a Programmable Chip (SOPC). The programmable logic fabric comprises any number of uncommitted gates and programmable interconnects between these gates so that they can be later programmed to perform specific functions. An MSA architecture allows digital logic to be designed and programmed using both small-scale block (e.g., gate level blocks) and/or medium scale block (e.g., Register Transfer Level, or “RTL,” blocks) techniques.
In an MSA architecture optimized for simple arithmetic operations, such as binary addition, subtraction, Boolean logic functions, etc., the CALUs can provide results expeditiously.
When designing a programmable logic device (PLD), a strategy is desired for placing objects derived from a high level language onto the PLD architecture. Many prior art attempts do not place those objects into PLDs efficiently and quickly. These prior art attempts often involve software that, due to the algorithms, takes an inordinate amount of time to run.
Thus, an improved system and method for programmable logic technology mapping and placement is desired.